James E. Davis
25Patents
4h-index
18Co-inventors
56Inventor score
Filing activity: Nov 22, 2011 → Aug 29, 2022
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US10128229B1 | Semiconductor devices with package-level configurability | Electricity | 9 | Active |
| US10312232B1 | Semiconductor devices with package-level configurability | Electricity | 6 | Active |
| US10483241B1 | Semiconductor devices with through silicon vias and package-level configurability | Electricity | 6 | Active |
| US10283462B1 | Semiconductor devices with post-probe configurability | Electricity | 4 | Active |
| US10580767B2 | Semiconductor devices with package-level configurability | Electricity | 2 | Active |
| US9281682B2 | Apparatuses and method for over-voltage event protection | Electricity | 2 | Active |
| US10193334B2 | Apparatuses and method for over-voltage event protection | Electricity | 2 | Active |
| US9391062B2 | Apparatuses, circuits, and methods for protection circuits for dual-direction nodes | Electricity | 1 | Active |
| US10403585B2 | Semiconductor devices with post-probe configurability | Electricity | 1 | Active |
| US11424169B2 | Memory device including circuitry under bond pads | Electricity | 1 | Active |
| US10867991B2 | Semiconductor devices with package-level configurability | Electricity | 1 | Active |
| US10784192B2 | Semiconductor devices having 3-dimensional inductive structures | Electricity | 1 | Active |
| US11901727B2 | Apparatuses and method for over-voltage event protection | Electricity | 0 | Active |
| US10811372B2 | Semiconductor devices with post-probe configurability | Electricity | 0 | Active |
| US11398468B2 | Apparatus with voltage protection mechanism | Physics | 0 | Active |
| US11798935B2 | Apparatus with voltage protection mechanism | Physics | 0 | Active |
| US12362244B2 | Memory device including circuitry under bond pads | Electricity | 0 | Active |
| US11508657B2 | Semiconductor devices having 3-dimensional inductive structures | Electricity | 0 | Active |
| US11848323B2 | Semiconductor devices with package-level configurability | Electricity | 0 | Active |
| US10453829B2 | Method and apparatus for reducing capacitance of input/output pins of memory device | Electricity | 0 | Active |
| US10930645B2 | Semiconductor devices with package-level configurability | Electricity | 0 | Active |
| US11183837B2 | Apparatuses and method for over-voltage event protection | Electricity | 0 | Active |
| US11056467B2 | Semiconductor devices with through silicon vias and package-level configurability | Electricity | 0 | Active |
| US12354669B2 | Discharge circuits | Physics | 0 | Active |
| US11908812B2 | Multi-die memory device with peak current reduction | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.