Ferroelectric non-volatile memory
US10453862B1 · kind B1 · utility
1Cited by
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7Claims
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Key dates
| Filing date | Mar 28, 2018 |
| Grant date | Oct 22, 2019 |
| Priority date | — |
| Expiry date | Mar 28, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B51/20
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory cell is provided that includes a control gate, a tunneling layer, a charge storage region, a blocking layer including a ferroelectric material, a semiconductor channel, and a source region and a drain region each disposed adjacent the semiconductor channel. The tunneling layer is disposed between the control gate and the charge storage region, the charge storage region is disposed between the tunneling layer and the blocking layer, and the blocking layer is disposed above the semiconductor channel.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.