High lateral to vertical ratio etch process for device manufacturing
US10460921B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 6, 2013 |
| Grant date | Oct 29, 2019 |
| Priority date | — |
| Expiry date | Nov 26, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/32139
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A layer stack over a substrate is etched using a photoresist pattern deposited on the layer stack as a first mask. The photoresist pattern is in-situ cured using plasma. At least a portion of the photoresist pattern can be modified by curing. In one embodiment, silicon by-products are formed on the photoresist pattern from the plasma. In another embodiment, a carbon from the plasma is embedded into the photoresist pattern. In yet another embodiment, the plasma produces an ultraviolet light to cure the photoresist pattern. The cured photoresist pattern is slimmed. The layer stack is etched using the slimmed photoresist pattern as a second mask.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.