Thermally enhanced package to reduce thermal interaction between dies
US10461067B2 · kind B2 · utility
1Cited by
2References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 31, 2017 |
| Grant date | Oct 29, 2019 |
| Priority date | — |
| Expiry date | Oct 31, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15311
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of reducing heat flow between IC chips and the resulting device are provided. Embodiments include attaching plural IC chips to an upper surface of a substrate; forming a lid over the IC chips; and forming a slit through the lid at a boundary between adjacent IC chips.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.