Daniel G. Berger
23Patents
13h-index
54Co-inventors
84Inventor score
Filing activity: Aug 22, 1991 → Oct 9, 2019
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US5209817A | Selective plating method for forming integral via and wiring layers | Electricity | 212 | Expired |
| US6528145B1 | Polymer and ceramic composite electronic substrates | Emerging Cross-Sectional Technologies | 118 | Expired |
| US5300403A | Line width control in a radiation sensitive polyimide | Physics | 75 | Expired |
| US5775569A | Method for building interconnect structures by injection molded solder and structures built | Electricity | 68 | Expired |
| US6149122A | Method for building interconnect structures by injection molded solder and structures built | Electricity | 41 | Expired |
| US6529021B1 | Self-scrub buckling beam probe | Physics | 28 | Expired |
| US6020750A | Wafer test and burn-in platform using ceramic tile supports | Physics | 25 | Expired |
| US6133633A | Method for building interconnect structures by injection molded solder and structures built | Electricity | 21 | Expired |
| US7405247B2 | Conductive adhesive composition | Emerging Cross-Sectional Technologies | 20 | Active |
| US6127735A | Interconnect for low temperature chip attachment | Emerging Cross-Sectional Technologies | 19 | Expired |
| US7312261B2 | Thermal interface adhesive and rework | Emerging Cross-Sectional Technologies | 18 | Expired |
| US7255153B2 | High performance integrated MLC cooling device for high power density ICS and method for manufacturing | Emerging Cross-Sectional Technologies | 15 | Expired |
| US6340630B1 | Method for making interconnect for low temperature chip attachment | Emerging Cross-Sectional Technologies | 13 | Expired |
| US7393419B2 | Conductive adhesive rework method | Emerging Cross-Sectional Technologies | 13 | Active |
| US5310625A | Process for forming negative tone images of polyimides using base treatment of crosslinked polyamic ester | Physics | 11 | Expired |
| US7329439B2 | UV-curable solvent free compositions and use thereof in ceramic chip defect repair | Electricity | 11 | Expired |
| US9859262B1 | Thermally enhanced package to reduce thermal interaction between dies | Electricity | 7 | Active |
| US9886193B2 | Architecture and implementation of cortical system, and fabricating an architecture using 3D wafer scale integration | Electricity | 3 | Active |
| US6838009B2 | Rework method for finishing metallurgy on chip carriers | Electricity | 3 | Expired |
| US10818570B1 | Stacked semiconductor devices having dissimilar-sized dies | Electricity | 2 | Active |
| US10461067B2 | Thermally enhanced package to reduce thermal interaction between dies | Electricity | 1 | Active |
| US10613754B2 | Architecture and implementation of cortical system, and fabricating an architecture using 3D wafer scale integration | Electricity | 0 | Active |
| US10503402B2 | Architecture and implementation of cortical system, and fabricating an architecture using 3D wafer scale integration | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.