Epitaxial region for embedded source/drain region having uniform thickness
US10461155B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 14, 2017 |
| Grant date | Oct 29, 2019 |
| Priority date | — |
| Expiry date | Nov 14, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/85
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor structure including a source/drain region is disclosed. The source/drain region may include a first epitaxial region along at least one sidewall of the source/drain region having a substantially uniform sidewall thickness. The semiconductor structure may further include a gate structure adjacent and above the source/drain region wherein at least a portion of the first epitaxial region is positioned below a sidewall spacer of the gate structure. A method of forming a source/drain region including a first epitaxial region having a substantially uniform sidewall thickness is disclosed. The method may include forming a trench in a substrate adjacent to a gate structure, forming the first epitaxial region in the trench, forming a spacer material layer on the gate structure and on a portion of the first epitaxial region, and removing a portion of the first epitaxial region using the spacer material layer as a mask.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.