Vertical field effect transistors with self aligned gate and source/drain contacts

US10461174B1 · kind B1 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Cheng Chi · Jersey City, US
• Hao Tang · Slingerlands, US
• Ruilong Xie · Niskayuna, US

Key dates

• Filing date: Jun 27, 2018
• Grant date: Oct 29, 2019
• Expiry date: Jun 27, 2038

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/0188
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A method of forming a semiconductor device includes: forming a bottom source or drain (S/D) layer on a substrate; forming a bottom spacer layer on the bottom S/D layer; forming a vertical transistor channel on the bottom S/D; forming a high-k metal gate layer on sides of the vertical transistor channel and above the bottom S/D layer; forming a gate spacer on sides of the vertical transistor channel and on top of the high-k metal gate layer; covering the high-k metal gate layer, the vertical transistor channel and bottom S/D layer with an interlayer dielectric (ILD); forming with a non-self-aligned contact (SAC) etch a bottom S/D recess through the ILD to expose the bottom S/D layer, the etch removing at least portion of the gate spacer and the high-k metal gate layer; and forming a bottom S/D contact spacer on sides of the bottom S/D recess.