Asymmetric voltage ramp rate control
US10468111B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 30, 2018 |
| Grant date | Nov 5, 2019 |
| Priority date | — |
| Expiry date | Apr 30, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods reduce device peak current during a read operation by charging control lines of a first set of memory cells faster than control lines of a second set of memory cells while minimizing the channel gradient formed adjacent to a selected word line to suppress occurrences of an injection read disturb in a sense line channel. For example, a first set of memory cells are in a first location relative to a selected memory cell selected for sensing, and a second set of memory cells are in a second location relative to the selected memory cell. The charge device is configured to charge the first set of memory cells and the second set of memory cells. In some aspects, a rate of charging the first set of memory cells is different from a rate of charging the second set of memory cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.