Methods of forming perpendicular magnetic tunnel junction memory cells having vertical channels
US10468293B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 28, 2017 |
| Grant date | Nov 5, 2019 |
| Priority date | — |
| Expiry date | Apr 9, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/792
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a transistor, according to one embodiment, includes: forming an doped material, depositing an oxide layer on the doped material, depositing a conducting layer on the oxide layer, patterning the conducting layer to form at least two word lines, depositing a nitride layer above the at least two word lines, defining at least two hole regions, at each of the defined hole regions, etching down to the doped material through each of the respective word lines, thereby creating at least two holes, depositing a gate dielectric layer on the nitride layer and in the at least two holes, depositing a protective layer on the gate dielectric layer, etching in each of the at least two holes down to the doped material, and removing a remainder of the protective layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.