High resistivity silicon-on-insulator substrate comprising a charge trapping layer formed on a substrate with a rough surface
US10468294B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 31, 2017 |
| Grant date | Nov 5, 2019 |
| Priority date | — |
| Expiry date | Jan 31, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/28176
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A multilayer composite structure and a method of preparing a multilayer composite structure are provided. The multilayer composite structure comprises a semiconductor handle substrate having a minimum bulk region resistivity of at least about 500 ohm-cm and the front surface of the single crystal semiconductor handle substrate has a surface roughness of at least about 0.1 micrometers as measured according to the root mean square method over a surface area of at least 30 micrometers by 30 micrometers. The composite structure further comprises a charge trapping layer in contact with the front surface, the charge trapping layer comprising poly crystalline silicon, the poly crystalline silicon comprising grains having a plurality of crystal orientations; a dielectric layer in contact with the charge trapping layer; and a single crystal semiconductor device layer in contact with the dielectric layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.