Stacked auxiliary field-effect transistors with buffers for radio frequency applications
US10469072B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 26, 2017 |
| Grant date | Nov 5, 2019 |
| Priority date | — |
| Expiry date | Sep 26, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B1/38
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Disclosed herein are switching or other active FET configurations that implement a main-auxiliary branch design. Such designs include a circuit assembly for performing a switching function that includes a branch including a main path in parallel with an auxiliary path, both the main path and the auxiliary path having a plurality of field-effect transistors. The circuit assembly also includes a first gate bias network connected to the main path. The circuit assembly also includes a second gate bias network connected to a first subset of the plurality of FETs of the auxiliary path. The circuit assembly also includes a third gate bias network connected to a second subset of the plurality of FETs of the auxiliary path so that the third gate bias network switches on the auxiliary path when the main path is on for nonlinear cancellation, and switches off the auxiliary path when the main path is off to enable the branch to withstand maximum voltage swings.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.