Soft bit techniques for a data storage device
US10474525B2 · kind B2 · utility
6Cited by
9References
26Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 11, 2015 |
| Grant date | Nov 12, 2019 |
| Priority date | — |
| Expiry date | Mar 11, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/52
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data storage device includes a memory, a first module, and a second module. The first module is configured to sense data stored at the memory to generate a first set of soft bits having a first number of bits. The second module is configured to perform an operation using the first set of soft bits to generate a second set of soft bits having a second number of bits that is less than the first number of bits. In an illustrative implementation, the second set of soft bits is used in connection with a three-stage decoding process to decode a set of hard bits that represents the data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.