Patent · US Active

Parallel test structure

US10475677B2 · kind B2 · utility

1Cited by
1References
19Claims
0Family size

Assignee

Inventors

Key dates

Filing dateAug 22, 2017
Grant dateNov 12, 2019
Priority date
Expiry dateMar 30, 2038

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH01L22/34
  • WIPO fieldMeasurement
  • WIPO sectorInstruments

Abstract

An exemplary apparatus includes a testing module connected to, and providing a test voltage to, an integrated circuit containing devices under test. The testing module performs a time-dependent dielectric breakdown (TDDB) test on the devices under test. A decoder is connected to the devices under test and the testing module. The decoder selectively connects each device being tested to the testing module. Efuses are connected to a different one of the devices under test. The efuses separately electrically disconnect each of the devices under test from the test voltage upon failure of a corresponding device under test. Protection circuits are connected between the efuses and a ground voltage. Each protection circuit provides a shunt around the decoder upon failure of the device under test.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.