Via architecture for increased density interface

US10475736B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Aleksandar Aleksov · Chandler, US
• Arnab Sarkar · Calabasas, US
• Arghya Sain · Chandler, US
• Kristof Darmawikarta · Chandler, US
• Henning Braunisch · Chandler, US
• Prashant Parmar · Gilbert, US
• Sujit Sharan · Boise, US
• Johanna M. Swan · Scottsdale, US
• Feras Eid · Chandler, US

Key dates

• Filing date: Sep 28, 2017
• Grant date: Nov 12, 2019
• Expiry date: Sep 28, 2037

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/3011
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Aspects of the embodiments are directed to an IC chip that includes a substrate comprising a first metal layer, a second metal layer, and a ground plane residing on the first metal layer. The second metal layer can include a first signal trace, the first signal trace electrically coupled to a first signal pad residing in the first metal layer by a first signal via. The second metal layer can include a second signal trace, the second signal trace electrically coupled to a second signal pad residing in the first metal layer by a second signal via. The substrate can also include a ground trace residing in the second metal layer between the first signal trace and the second signal trace, the ground trace electrically coupled to the ground plane by a ground via. The vias coupled to the traces can include self-aligned or zero-misaligned vias.