Vertical gate-all-around transistor and manufacturing method thereof
US10475744B2 · kind B2 · utility
2Cited by
1References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 6, 2017 |
| Grant date | Nov 12, 2019 |
| Priority date | — |
| Expiry date | Oct 15, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes a substrate, an isolation structure, an outer structure, and a gate structure. The isolation structure is disposed on the substrate. The outer structure surrounds a sidewall of the isolation structure. The gate structure surrounds a central part of the outer structure, so that the central part covered by the gate structure becomes a channel region, and the outer structure at both sides of the central part respectively becomes a source region and a drain region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.