Pillar contact extension and method for producing the same
US10475990B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 22, 2018 |
| Grant date | Nov 12, 2019 |
| Priority date | — |
| Expiry date | Feb 12, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N50/80
Abstract
Methods of forming a pillar contact extension within a memory device using a self-aligned planarization process rather than direct ILD CMP and the resulting devices are provided. Embodiments include forming a photoresist layer over a low-K layer formed over an ILD having a first metal layer in a memory region and in a logic region and pillar-shaped conductors formed atop of the first metal layer only in the memory region; forming a trench through the photoresist layer over each pillar-shaped conductor; extending the trench through the low-K layer to an upper surface of each pillar-shaped conductor; forming a second metal layer over the low-K layer, filling the trench entirely; and planarizing the second metal layer until the second metal layer is removed from over the logic region, a pillar contact extension formed atop of each pillar-shaped conductor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.