Multi-state memory device and method for adjusting memory state characteristics of the same
US10482953B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 14, 2018 |
| Grant date | Nov 19, 2019 |
| Priority date | — |
| Expiry date | Aug 14, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B63/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multi-state memory device includes a first memory element, a second memory element, a first controlling element and a second controlling element. The second memory element has a memory cell structure identical to that of the first memory element and connects to the first memory element in series. The first controlling element is connected to the first memory element either in series or in parallel. The second controlling element has a characteristic value identical to that of the first controlling element and is connected to the second memory element by a connection structure identical to that of the first controlling element. When the first memory element receives a first signal and a second signal through the first controlling element, a first state value and a second state value are generated correspondingly, and the characteristic value is greater than the first state value and less than the second state value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.