Post-passivation interconnect structure and method of forming the same
US10483132B2 · kind B2 · utility
1Cited by
9References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 30, 2013 |
| Grant date | Nov 19, 2019 |
| Priority date | — |
| Expiry date | May 30, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes a passivation layer formed on a semiconductor substrate, a protective layer overlying the passivation layer and having an opening, an interconnect structure formed in the opening of the protective layer, a bump formed on the interconnect structure, and a molding compound layer overlying the interconnect structure and being in physical contact with a lower portion of the bump.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.