Method for manufacturing dual FinFET device
US10483167B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 15, 2017 |
| Grant date | Nov 19, 2019 |
| Priority date | — |
| Expiry date | Aug 15, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0147
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In a method for manufacturing a semiconductor device, a substrate is provided. A hard mask and a mask layer are formed on a first region and a second region of the substrate. The substrate is recessed using the hard mask and the mask layer to form a fin structure in the first region and a raised structure in the second region. First isolation structures and second isolation structures are formed on lower portions of opposite sidewalls of the fin structure and opposite sidewalls of the raised structure. A first gate structure is formed on a portion of the fin structure, and a second gate structure is formed on a portion of the raised structure. A first source and a first drain are formed on opposite sides of the first gate structure, and a second source and a second drain are formed on opposite sides of the second gate structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.