Embedded trace substrate structure and semiconductor package structure including the same
US10483196B2 · kind B2 · utility
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18Claims
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Inventor
Key dates
| Filing date | Feb 2, 2018 |
| Grant date | Nov 19, 2019 |
| Priority date | — |
| Expiry date | Feb 2, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15313
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A substrate structure includes a carrier, a first metal layer, a circuit layer and a dielectric layer. The carrier has a first surface and a second surface. The first metal layer is disposed on the first surface of the carrier. The circuit layer is disposed on the first metal layer. The dielectric layer covers the circuit layer and defines a plurality of openings to expose portions of the circuit layer and portions of the first metal layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.