High density memory architecture using back side metal layers
US10483321B2 · kind B2 · utility
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16Claims
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Key dates
| Filing date | Jun 2, 2015 |
| Grant date | Nov 19, 2019 |
| Priority date | — |
| Expiry date | Jun 2, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/71
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A microelectronic memory having metallization layers formed on a back side of a substrate, wherein the metallization layers on back side may be used for the formation of source lines and word lines. Such a configuration may allow for a reduction in bit cell area, a higher memory array density, and lower source line and word line resistances. Furthermore, such a configuration may also provide the flexibility to independently optimize interconnect performance for logic and memory circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.