Embedded MRAM in interconnects and method for producing the same
US10483461B2 · kind B2 · utility
3Cited by
3References
10Claims
0Family size
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Key dates
| Filing date | Apr 19, 2018 |
| Grant date | Nov 19, 2019 |
| Priority date | — |
| Expiry date | Apr 19, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N50/80
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Method of forming embedded MRAM in interconnects using a metal hard mask process and the resulting device are provided. Embodiments include forming a first interlayer dielectric (ILD) layer including a first metal (Mx) level; forming a capping layer over the first ILD layer; forming magnetic tunnel junction (MTJ) structures formed in a second ILD over the first capping layer; forming a second metal (Mx+1) level in the second ILD layer; forming a second capping layer over the second ILD layer; and forming a third metal (Mx+2) level in a third ILD layer over the second capping layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.