Memory system with on-the-fly error detection and termination and operating method thereof
US10484008B2 · kind B2 · utility
4Cited by
1References
18Claims
0Family size
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Key dates
| Filing date | Sep 28, 2017 |
| Grant date | Nov 19, 2019 |
| Priority date | — |
| Expiry date | Jan 30, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/09
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Decoding method includes calculating cyclic redundancy check (CRC) parity bits for data on-the-fly; performing a low-density parity-check (LDPC) decoding for the data; if it is determined that an iteration of is finished, updating the calculated CRC parity bits to generate CRC parity bits; comparing the generated CRC parity bits with CRC bits included in the data; and terminating the LDPC decoding based on the comparison result.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.