Semiconductor structure with contact plug and method of fabricating the same
US10490557B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Mar 7, 2018 |
| Grant date | Nov 26, 2019 |
| Priority date | — |
| Expiry date | Mar 7, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/34
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor structure having a contact plug includes a substrate. A memory cell region and a peripheral circuit region are defined on the substrate. At least one memory cell is disposed on the substrate within the memory cell region. The memory cell includes a transistor and a capacitor structure. A first planar stacked dielectric layer covers the peripheral circuit region. The first planar stacked dielectric layer includes two first dielectric layers and a second dielectric layer. The first dielectric layer at the bottom of the first planar stacked dielectric layer extends to the memory cell region and covers the capacitor structure. A contact plug is disposed at the peripheral circuit region and penetrates the first planar stacked dielectric layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.