Low-k gate spacer and methods for forming the same
US10490650B2 · kind B2 · utility
0Cited by
1References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 14, 2017 |
| Grant date | Nov 26, 2019 |
| Priority date | — |
| Expiry date | Nov 14, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/017
Abstract
Embodiments of the present disclosure relate to a FinFET device having gate spacers with reduced capacitance and methods for forming the FinFET device. Particularly, the FinFET device according to the present disclosure includes gate spacers formed by two or more depositions. The gate spacers are formed by depositing first and second materials at different times of processing to reduce parasitic capacitance between gate structures and contacts introduced after epitaxy growth of source/drain regions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.