Deep learning for low-density parity-check (LDPC) decoding
US10491243B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 26, 2017 |
| Grant date | Nov 26, 2019 |
| Priority date | — |
| Expiry date | Sep 11, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/45
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Techniques for improving the bit error rate (BER) performance of an error correction system are described. In an example, the error correction system implements low-density parity-check (LDPC) decoding that uses bit flipping. In a decoding iteration, a feature map is generated for a bit of an LDPC codeword. The bit corresponds to a variable node. The feature map is input to a neural network that is trained to determine whether bits should be flipped based on corresponding feature maps. An output of the neural network is accessed. The output indicates that the bit should be flipped based on the feature map. The bit is flipped in the decoding iteration based on the output of the neural network.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.