Efficient hardware-based extraction of program instructions for critical paths
US10496413B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 15, 2017 |
| Grant date | Dec 3, 2019 |
| Priority date | — |
| Expiry date | Jul 10, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F8/41
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor includes a memory to hold a buffer to store data dependencies comprising nodes and edges for each of a plurality of micro-operations. The nodes include a first node for dispatch, a second node for execution, and a third node for commit. A detector circuit is to queue, in the buffer, the nodes of a micro-operation; add, to determine a node weight for each of the nodes of the micro-operation, an edge weight to a previous node weight of a connected micro-operation that yields a maximum node weight for the node, wherein the node weight comprises a number of execution cycles of an OOO pipeline of the processor and the edge weight comprises a number of execution cycles to execute the connected micro-operation; and identify, as a critical path, a path through the data dependencies that yields the maximum node weight for the micro-operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.