System level simulation in Network on Chip architecture
US10496770B2 · kind B2 · utility
Inventors
Key dates
| Filing date | Sep 14, 2016 |
| Grant date | Dec 3, 2019 |
| Priority date | — |
| Expiry date | Feb 21, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2115/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods for performing multi-message transaction based performance simulations of SoC IP cores within a Network on Chip (NoC) interconnect architecture by accurately imitating full SoC behavior are described. The example implementations involve simulations to evaluate and detect NoC behavior based on execution of multiple transactions at different rates/times/intervals, wherein each transaction can contain one or more messages, with each message being associated with a source agent and a destination agent. Each message can also be associated with multiple parameters such as rate, size, value, latency, among other like parameters that can be configured to indicate the execution of the transaction by a simulator to simulate a real-time scenario for generating performance reports for the NoC interconnect.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.