Dual gate memory devices
US10497415B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 8, 2018 |
| Grant date | Dec 3, 2019 |
| Priority date | — |
| Expiry date | Jan 8, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B61/22
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The various implementations described herein include methods, devices, and systems for performing operations on memory devices. In one aspect, a memory device includes: (1) a first charge storage device having a first gate with a corresponding first threshold voltage, the first charge storage device configured to store charge corresponding to one or more first bits; and (2) a second charge storage device having a second gate with a corresponding second threshold voltage, distinct from the first threshold voltage, the second charge storage device configured to store charge corresponding to one or more second bits; where the second charge storage device is coupled in parallel with the first charge storage device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.