Method of manufacturing a dopant transistor located vertically on the gate
US10497627B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 1, 2017 |
| Grant date | Dec 3, 2019 |
| Priority date | — |
| Expiry date | Jul 29, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method is provided for forming a transistor from a stack including the following successive layers: an electrically insulating layer, an active zone including at least one semiconductor layer, and a gate, sides of which are configured to be covered by at least one spacer, the method including: a phase of forming lateral cavities; and forming a raised drain and a raised source that fill the lateral cavities by growing the semiconductor layer via epitaxy, the forming of the lateral cavities includes, after a step of partially removing the semiconductor layer: forming a sacrificial layer, partially removing the sacrificial layer; forming spacers against the sides of the gate resting on a residual sacrificial layer; and totally removing the residual sacrificial layer in order to form the lateral cavities.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.