Inventor · Dijon, FR

Perrine Batude

24Patents

4h-index

25Co-inventors

59Inventor score

Filing activity: May 15, 2009 → Sep 16, 2021

Most-cited inventions

Patent	Title	Area	Cited by	Status
US8183630B2	Circuit with transistors integrated in three dimensions and having a dynamically adjustable threshold voltage VT	Electricity	252	Active
US8013399B2	SRAM memory cell having transistors integrated at several levels and the threshold voltage VT of which is dynamically adjustable	Electricity	228	Active
US8853785B2	Integrated circuit with electrostatically coupled MOS transistors and method for producing such an integrated circuit	Electricity	179	Active
US9502566B2	Method for producing a field effect transistor including forming a gate after forming the source and drain	Electricity	9	Active
US9246006B2	Recrystallization of source and drain blocks from above	Electricity	4	Active
US9018078B2	Method of making a 3D integrated circuit	Electricity	3	Active
US9379213B2	Method for forming doped areas under transistor spacers	Electricity	2	Active
US9343375B2	Method for manufacturing a transistor in which the strain applied to the channel is increased	Electricity	2	Active
US9966453B2	Method for doping source and drain regions of a transistor by means of selective amorphisation	Electricity	2	Active
US10170621B2	Method of making a transistor having a source and a drain obtained by recrystallization of semiconductor	Electricity	2	Active
US9761607B2	Method for producing strained semi-conductor blocks on the insulating layer of a semi-conductor on insulator substrate	Electricity	2	Active
US11658260B2	Method of manufacturing an optoelectronic device comprising a plurality of diodes	Electricity	1	Active
US10586740B2	Method for manufacturing pairs of CMOS transistors of the “fin-FET” type at low temperatures	Electricity	1	Active
US8722471B2	Method for forming a via contacting several levels of semiconductor layers	Electricity	1	Active
US10553702B2	Transistor with controlled overlap of access regions	Electricity	0	Active
US12154930B2	Three-dimensional microelectronic circuit with optimised distribution of its digital and analogue functions	Electricity	0	Active
US10651202B2	3D circuit transistors with flipped gate	Electricity	0	Active
US11011425B2	Production of a 3D circuit with upper level transistor provided with a gate dielectric derived from a substrate transfer	Electricity	0	Active
US11888007B2	Image sensor formed in sequential 3D technology	Electricity	0	Active
US10319628B2	Integrated circuit having a plurality of active layers and method of fabricating the same	Electricity	0	Active
US11139209B2	3D circuit provided with mesa isolation for the ground plane zone	Electricity	0	Active
US11552125B2	Method of manufacturing an optoelectronic device comprising a plurality of diodes and an electronic circuit for controlling these diodes	Electricity	0	Active
US9779982B2	Fabrication method of a stack of electronic devices	Electricity	0	Active
US10497627B2	Method of manufacturing a dopant transistor located vertically on the gate	Electricity	0	Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.