Patent · US Active

Power semiconductor arrangement having a stack of connection plates

US10497684B2 · kind B2 · utility

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0References

20Claims

0Family size

Assignee

Infineon Technologies AG · DE

Inventors

Matthias Wissen · Wadersloh, DE
Daniel Domes · Schwäbisch Hall, DE
Andreas Groove · Ottobeuren, DE

Key dates

Filing date	Apr 19, 2018
Grant date	Dec 3, 2019
Priority date	—
Expiry date	Apr 19, 2038

Classification

Technology area (CPC H)Electricity
CPC primaryH01L25/117
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

A power semiconductor arrangement includes a plurality of half-bridges arranged in parallel alongside one another by way of a longer longitudinal side of the half-bridges. An input load current terminal, an output load current terminal and a phase terminal are arranged on a top side of each of the half-bridges, the input load current terminals and the output load current terminals being arranged on an imaginary line that runs orthogonal to the longer longitudinal side of the half-bridges. First connection plates are connected to respective ones of the output load current terminals, and second connection plates are connected to respective ones of the input load current terminals. The first connection plates are arranged above the second connection plates. The first and the second connection plates are arranged in parallel with one another and electrically insulated from one another.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.