Memory structure and forming method thereof
US10497708B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 12, 2018 |
| Grant date | Dec 3, 2019 |
| Priority date | — |
| Expiry date | Sep 12, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/30105
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A memory structure provided by this invention includes a first substrate, a dielectric layer, a bonding pad, and an isolation structure. The first substrate includes a substrate layer and a memory layer. The substrate layer has opposite first and second surfaces, the memory layer is located on the first surface of the substrate layer, and the first substrate includes a bonding pad region. The dielectric layer is disposed on the second surface of the substrate layer. The bonding pad is disposed on the surface of the dielectric layer in the bonding pad region. The isolation structure penetrates through the substrate layer and is disposed at the edge of the bonding pad region and surrounds the substrate layer in the bonding pad region, and the isolation structure is used for isolating the substrate layer in the bonding pad region from the substrate layer at the periphery of the isolation structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.