Data dependency mitigation in parallel decoders for flash storage
US10498366B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 28, 2017 |
| Grant date | Dec 3, 2019 |
| Priority date | — |
| Expiry date | Jun 4, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/1545
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A memory device can include a memory array, a processor coupled to the memory array, and a decoding apparatus. The decoding apparatus is configured to perform parallel decoding of codewords. Each of the codewords has a plurality of data blocks, each data block having a number of data bits. The decoding apparatus is configured to decode in parallel two or more codewords, which share a common data block, to determine error information associated with each codeword. For each error, the error information identifies a data block having the and associated error bit patterns. The decoding apparatus is configured to update the two or more codewords based on the identified data blocks having errors and the associated error bit patterns.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.