Progressive effort decoder architecture
US10498367B2 · kind B2 · utility
1Cited by
5References
20Claims
0Family size
Assignee
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Key dates
| Filing date | Apr 19, 2017 |
| Grant date | Dec 3, 2019 |
| Priority date | — |
| Expiry date | Aug 23, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/3715
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A memory device may include memory components to store data. The memory device may also include a processor that may decode a codeword associated with the data. The processor may receive the codeword and determine whether the codeword is independently decodable using a BCH decoder. The processor may then decode the codeword using the BCH decoder when the codeword is determined to be independently decodable using the BCH decoder. Otherwise, the processor may decode the codeword using a second decoder and the BCH decoder when the codeword is not determined to be independently decodable using the BCH decoder.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.