Robert B. Eisenhuth
25Patents
5h-index
11Co-inventors
66Inventor score
Filing activity: Jan 29, 1993 → Oct 11, 2022
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US5436887A | Digital full-duplex transceiver | Electricity | 13 | Expired |
| US9064575B2 | Determining whether a memory cell state is in a valley between adjacent data states | Physics | 8 | Active |
| US8627165B2 | Bitwise operations and apparatus in a multi-level system | Electricity | 6 | Active |
| US8615703B2 | Advanced bitwise operations and apparatus in a multi-level system with nonvolatile memory | Electricity | 5 | Active |
| US11494114B1 | Read threshold adjustment techniques for non-binary memory cells | Physics | 5 | Active |
| US10997070B1 | Efficient scrambling and encoding for copyback procedures using precomputed values | Physics | 4 | Active |
| US8522087B2 | Advanced converters for memory cell sensing and methods | Electricity | 2 | Active |
| US8782474B2 | Advanced converters for memory cell sensing and methods | Electricity | 2 | Active |
| US11443828B1 | Read threshold adjustment techniques for memory | Physics | 2 | Active |
| US9990988B2 | Determining whether a memory cell state is in a valley between adjacent data states | Physics | 2 | Active |
| US9654144B2 | Progressive effort decoder architecture | Electricity | 2 | Active |
| US9411675B2 | Advanced bitwise operations and apparatus in a multi-level system with nonvolatile memory | Electricity | 1 | Active |
| US10740173B2 | Advanced bitwise operations and apparatus in a multi-level system with nonvolatile memory | Electricity | 1 | Active |
| US10498367B2 | Progressive effort decoder architecture | Electricity | 1 | Active |
| US10923211B1 | Efficient scrambling and encoding for copyback procedures in a memory subsystem | Physics | 1 | Active |
| US10811090B2 | Memory cell state in a valley between adjacent data states | Physics | 1 | Active |
| US11789817B2 | Error correction for internal read operations | Electricity | 1 | Active |
| US11854641B2 | Read threshold adjustment techniques for memory | Physics | 0 | Active |
| US11416393B2 | Efficient scrambling and encoding for copyback procedures using precomputed values | Physics | 0 | Active |
| US11934688B2 | Read threshold adjustment techniques for non-binary memory cells | Physics | 0 | Active |
| US11804856B2 | Advanced bitwise operations and apparatus in a multi-level system with nonvolatile memory | Electricity | 0 | Active |
| US10355815B2 | Bitwise operations and apparatus in a multi-level system | Electricity | 0 | Active |
| US11336303B2 | Advanced bitwise operations and apparatus in a multi-level system with nonvolatile memory | Electricity | 0 | Active |
| US9374343B2 | Bitwise operations and apparatus in a multi-level system | Electricity | 0 | Active |
| US11450382B2 | Memory cell state in a valley between adjacent data states | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.