Cache to cache data transfer acceleration techniques
US10503648B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 12, 2017 |
| Grant date | Dec 10, 2019 |
| Priority date | — |
| Expiry date | Feb 23, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/62
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems, apparatuses, and methods for accelerating cache to cache data transfers are disclosed. A system includes at least a plurality of processing nodes and prediction units, an interconnect fabric, and a memory. A first prediction unit is configured to receive memory requests generated by a first processing node as the requests traverse the interconnect fabric on the path to memory. When the first prediction unit receives a memory request, the first prediction unit generates a prediction of whether data targeted by the request is cached by another processing node. The first prediction unit is configured to cause a speculative probe to be sent to a second processing node responsive to predicting that the data targeted by the memory request is cached by the second processing node. The speculative probe accelerates the retrieval of the data from the second processing node if the prediction is correct.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.