Data block sizing for channels in a multi-channel high-bandwidth memory
US10503655B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 21, 2016 |
| Grant date | Dec 10, 2019 |
| Priority date | — |
| Expiry date | Nov 14, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/60
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The described embodiments include a computing device that caches data acquired from a main memory in a high-bandwidth memory (HBM), the computing device including channels for accessing data stored in corresponding portions of the HBM. During operation, the computing device sets each of the channels so that data blocks stored in the corresponding portions of the HBM include corresponding numbers of cache lines. Based on records of accesses of cache lines in the HBM that were acquired from pages in the main memory, the computing device sets a data block size for each of the pages, the data block size being a number of cache lines. The computing device stores, in the HBM, data blocks acquired from each of the pages in the main memory using a channel having a data block size corresponding to the data block size for each of the pages.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.