Neural network accelerator with parameters resident on chip
US10504022B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 9, 2018 |
| Grant date | Dec 10, 2019 |
| Priority date | — |
| Expiry date | Aug 9, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06N3/0499
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
One embodiment of an accelerator includes a computing unit; a first memory bank for storing input activations and a second memory bank for storing parameters used in performing computations, the second memory bank configured to store a sufficient amount of the neural network parameters on the computing unit to allow for latency below a specified level with throughput above a specified level. The computing unit includes at least one cell comprising at least one multiply accumulate (“MAC”) operator that receives parameters from the second memory bank and performs computations. The computing unit further includes a first traversal unit that provides a control signal to the first memory bank to cause an input activation to be provided to a data bus accessible by the MAC operator. The computing unit performs computations associated with at least one element of a data array, the one or more computations performed by the MAC operator.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.