Lithographic patterning to form fine pitch features
US10504774B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 20, 2016 |
| Grant date | Dec 10, 2019 |
| Priority date | — |
| Expiry date | Apr 8, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/53238
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods of lithographic patterning to form interconnect structures for a chip. A hardmask layer is formed on a dielectric layer. A sacrificial layer is formed on the hardmask layer. First opening and second openings are formed in the sacrificial layer that extend through the sacrificial layer to the hardmask layer. A resist layer is formed on the sacrificial layer. An opening is formed in the resist layer that is laterally located between the first opening in the first sacrificial layer and the second opening in the first sacrificial layer. The resist layer is comprised of a metal oxide resist material that is removable selective to the hardmask layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.