Integrated circuit comprising balanced cells at the active

US10504897B2 · kind B2 · utility

Assignees

• COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES · FR
• STMicroelectronics (Crolles 2) SAS · FR

Inventors

• Francois Andrieu · Meylan, FR
• Remy BERTHELON · Crolles, FR

Key dates

• Filing date: Sep 18, 2017
• Grant date: Dec 10, 2019
• Expiry date: Sep 18, 2037

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D62/832

Abstract

An integrated circuit is provided, including a first pair including a first nMOS transistor and a first pMOS transistor; a second pair including a second nMOS transistor and a second pMOS transistor; the first and second pMOS transistors including a channel that is subjected to compressive stress and made of an SiGe alloy, and a gate of said transistors being positioned at least 250 nm from a border of an active zone of said transistors; a third pair including a third nMOS transistor having a same construction as the first nMOS transistor and a third pMOS transistor having a same construction as the second pMOS transistor and exhibiting a compressive stress that is lower by at least 250 MPa, the gate of said transistors of the third pair being positioned at most 200 nm from the border.