Memory device with dynamic cache management

US10509722B2 · kind B2 · utility

Assignee

• Micron Technology, Inc. · US

Inventors

• Kishore Kumar Muchherla · Fremont, US
• Peter Feeley · Boise, US
• Ashutosh Malshe · Fremont, US
• Daniel J. Hubbard · Boise, US
• Christopher S. Hale · Boise, US
• Kevin R. Brandt · Boise, US
• Sampath K. Ratnam · Boise, US
• Yun Li · Fremont, US
• Marc S. Hamilton · Eagle, US

Key dates

• Filing date: Aug 31, 2017
• Grant date: Dec 17, 2019
• Expiry date: Nov 1, 2037

Classification

• Technology area (CPC G): Physics
• CPC primary: G11C2211/5641
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A memory system includes a memory array having a plurality of memory cells; and a controller coupled to the memory array, the controller configured to: select a garbage collection (GC) source block storing valid data, calculate a valid data measure for the GC source block for representing an amount of the valid data within the GC source block, and designate a storage mode for an available memory block based on the valid data measure, wherein the storage mode is for controlling a number of bits stored per each of the memory cells for subsequent or upcoming data writes.