Method and apparatus for interrupting memory bank refresh
US10510396B1 · kind B1 · utility
34Cited by
4References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 19, 2018 |
| Grant date | Dec 17, 2019 |
| Priority date | — |
| Expiry date | Jun 19, 2038 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory controller includes a state machine that initiates a memory refresh of a DRAM (having a number of banks) by sending thereto a refresh command. Responsive to receiving the command, the DRAM may perform a per-bank refresh in which individual ones of the banks are refreshed in succession, one at a time. Upon receiving a high priority transaction, a determination is made as to the number of memory banks that have currently been refreshed in the per-bank refresh. If the number of banks refreshed is less than a threshold value, the per-bank refresh is aborted.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.