High voltage integration for HKMG technology
US10510750B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 13, 2018 |
| Grant date | Dec 17, 2019 |
| Priority date | — |
| Expiry date | Aug 13, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/856
Abstract
The present disclosure relates to an integrated circuit (IC) and a method of formation. In some embodiments, a first transistor gate stack is disposed in a low voltage region defined on a substrate. The first transistor gate stack comprises a first gate electrode and a first gate dielectric separating the first gate electrode from the substrate. A third transistor gate stack is disposed in a high voltage region defined on the substrate. The third transistor gate stack comprises a third gate electrode and a third gate dielectric separating the third gate electrode from the substrate. The third gate dielectric comprises an oxide component and a first interlayer dielectric layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.