Semiconductor memory device and manufacturing method thereof
US10510758B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 4, 2017 |
| Grant date | Dec 17, 2019 |
| Priority date | — |
| Expiry date | Dec 26, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/693
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A manufacturing method of a semiconductor memory device includes the following steps. A gate structure is formed on a semiconductor substrate. The gate structure includes a floating gate electrode, a control gate electrode, a first oxide layer, and a second oxide layer. The control gate electrode is disposed on the floating gate electrode. The first oxide layer is disposed between the floating gate electrode and the semiconductor substrate. The second oxide layer is disposed between the floating gate electrode and the control gate electrode. An oxide spacer layer is conformally on the gate structure and the semiconductor substrate. A nitride spacer is formed on the oxide spacer layer and on a sidewall of the gate structure. An oxidation process is performed after the step of forming the nitride spacer. A thickness of an edge portion of the first oxide layer is increased by the oxidation process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.