Patent · US Active

Staircase etch control in forming three-dimensional memory device

US10522474B2 · kind B2 · utility

1Cited by
7References
19Claims
0Family size

Assignee

Inventors

Key dates

Filing dateJul 26, 2018
Grant dateDec 31, 2019
Priority date
Expiry dateJul 26, 2038

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH10B43/50
  • WIPO fieldSemiconductors
  • WIPO sectorElectrical engineering

Abstract

Embodiments of three-dimensional (3D) memory devices and methods for controlling a photoresist (PR) trimming rate in the formation of the 3D memory devices are disclosed. In an example, a method includes forming a dielectric stack over a substrate, measuring a first distance between the first trimming mark and the PR layer along a first direction, and trimming the PR layer along the first direction. The method also includes etching the dielectric stack using the trimmed PR layer as an etch mask to form a staircase, forming a second trimming mark using the first trimming mark as an etch mask, measuring a second distance between the second trimming mark and the trimmed PR layer, comparing the first distance with the second distance to determine a difference between an actual PR trimming rate and an estimated PR trimming rate, and adjusting PR trimming parameters based on the difference.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.