Automatic performance characterization of a network-on-chip (NOC) interconnect
US10528682B2 · kind B2 · utility
1Cited by
29References
20Claims
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Key dates
| Filing date | Sep 4, 2014 |
| Grant date | Jan 7, 2020 |
| Priority date | — |
| Expiry date | Feb 17, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods, systems, and non-transitory computer readable medium for automatically characterizing performance of a System-on-Chip (SoC) and/or Network-on-Chip (NoC) with respect to latency and throughput attributes of one or more traffic flows/profiles under varying traffic load conditions. The characterization of performance may involve a plot representative of latency and throughput, depending on the desired implementation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.