Reduction of ZQ calibration time
US10529390B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 30, 2018 |
| Grant date | Jan 7, 2020 |
| Priority date | — |
| Expiry date | Nov 30, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2254
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory system includes an external calibration device that has a predetermined impedance and a first memory device with a first pad for selective connection to the external calibration device. The first memory device also includes an internal calibration device having an impedance that is programmable and a second pad connected to the internal calibration device. The system further includes a second memory device having a third pad for selective connection to the second pad of the first memory device. A processing device is operatively coupled to the first memory device and the second memory device. The processing device programs the impedance of the internal calibration device of the first memory device based on the external calibration device, and programs an impedance of a termination component in the second memory device based on the impedance of the internal calibration device of the first memory device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.