Semiconductor memory device in which different upper limit values are set for pass voltages
US10529731B2 · kind B2 · utility
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12Claims
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Key dates
| Filing date | Mar 1, 2018 |
| Grant date | Jan 7, 2020 |
| Priority date | — |
| Expiry date | Mar 1, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0483
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device includes a first memory cell transistor, a second memory cell transistor, and a third memory cell transistor that are connected in series. A word line is coupled to a gate of the third memory cell transistor. A controller is configured to set a first upper limit value for voltages applied to the word line during writing of data to the first memory cell transistor and a second upper limit value for voltages applied to the word line during writing of data to the second memory cell transistor. The second upper limit value is different from the first upper limit value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.