High speed frequency divider
US10530375B1 · kind B1 · utility
5Cited by
11References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 5, 2018 |
| Grant date | Jan 7, 2020 |
| Priority date | — |
| Expiry date | Sep 5, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K21/08
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A frequency divider circuit (200) includes a frequency sub-divider (201) to provide a frequency divided clock, a delay circuit (250) configured to delay the frequency divided clock by N+0.5 cycles of the input clock to generate a delayed clock, and an output circuit (202) configured to generate an output clock based on the frequency divided clock and the delayed clock, where the output clock has a frequency that is equal to 1/(N+0.5) times a frequency of the input clock, and N is an integer greater than one.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.